DK-DEV-5SGXEA7N【PDF 269/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51011

2014.01.10

Figure 9-6: Timing Requirements

Testing the Error Detection Block

9-9

Frame

Data Integrity

N

No CRC Error

N+1

CRC Error

N+2

CRC Error

N+3

No CRC Error

N+4

CRC Error

N+5

No CRC Error

Read Data Frame

CRC ERROR Pin

CRC Calculation

(minimum 32 clock

cycles)

Read Error Message

Register (allowed time)

Read Error Message

for frame N+1

Read Error Message

for frame N+2

Read Error Message

for frame N+4

Retrieving Error Information

You can retrieve the error information via the core interface or the JTAG interface using the

SHIFT_EDERROR_REG JTAG instruction.

Recovering from CRC Errors

The system that hosts the FPGA must control device reconfiguration. To recover from a CRC error, drive

the nCONFIG signal low. The system waits for a safe time before reconfiguring the device. When reconfiguration

completes successfully, the FPGA operates as intended.

Related Information

? Error Detection Frequency on page 9-3

Provides more information about the minimum and maximum error detection frequencies.

? Minimum EMR Update Interval on page 9-2

Provides more information about the duration of each Stratix Vdevice.

? Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices

Provides more information about how to retrieve the error information.

Testing the Error Detection Block

You can inject errors into the configuration data to test the error detection block. This error injection

methodology provides design verification and system fault tolerance characterization.

Testing via the JTAG Interface

You can intentionally inject single or double-adjacent errors into the configuration data using the

EDERROR_INJECT JTAG instruction.

SEU Mitigation for Stratix V Devices

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